1. Field of the Invention
The present invention relates to paging storage systems employing a backing store such as a DASD (Direct Access Storage Device) and a front store, serving as a cache, and preferably consisting of a random access memory system.
2. Description of the Prior Art
Paging and swapping stores have taken several configurations, one of which involves using various direct access storage devices directly for storing paging and swapping data. The problem concerned with using such devices is the relatively long access time to stored paging and swapping data which has an adverse effect on the total central processing unit or data processing system performance; that is, such paging and swapping storage usually stores instructions to be executed by the central processing unit or data processing system. Accordingly, it is extremely important that such programs of instructions be promptly accessed for enhancing execution of such instructions. The IBM 2305 Fixed Head Storage Module described in publication GA-26-1589, available from International Business Machines Corporation, Armonk, N.Y., describes a storage drum for use in a paging and swapping environment. An advantage of the storage drum over and above the direct access storage devices is the relatively fast access to the paging and swapping instruction signals. A disadvantage is the relatively high cost for a given capacity of the storage drum. Accordingly, in many paging and swapping applications, a storage drum such as the IBM 2305 unit stores active pages of instruction data, while the relatively inactive instruction data is kept on direct access storage devices. Transferring the instruction data from the direct access storage device to the storage drum usually involves taking the units offline such that instruction execution time is not impacted. Accordingly, a hierarchical paging storage system which automatically transfers instruction data in the form of paging and swapping data sets between a front store, which has high speed accesses, and a backing store, having relatively large capacity and lower cost, hence a longer access, is desired. Further, multiple exposures to the data are to be provided; that is, more than one address should be usable to access a given unit of data. In this regard, the IBM 2305 unit supports multiple requesting in that addresses 0-7 cause access to a magnetic storage drum having a physical address of 0, while addresses in the group 8-15 select the drum module having a physical address 8. Each drum, of course, can honor only one access at a given time; therefore, a given access through one of the addresses for a given drum module will place all of the addresses to that given drum module in a so-called nonaccessible state. A greater flexibility in the multiple addressing area is highly desired for enhancing execution of programs of instructions stored and furnished in the form of paging and swapping data sets.
Hierarchical stores for diverse applications have been employed with diverse backing stores; for example, backing stores can be in the form of magnetic tape recorders, magnetic disk storage apparatus such as direct access storage devices (DASD), relatively slow random access memories, magnetic bubble or shift register type of memories, record library systems and the like. Front stores, which are designed to mask the relatively long access times to a backing store, have also taken diverse types of configurations. For example, in the IBM 3850 Mass Storage System, a backing store consisted of a magnetic tape library, while a front store consisted of a plurality of direct access storage devices. Here, the access to the direct access storage devices was relatively fast when compared with access to data in a data cartridge contained in the automatic tape library. Further, in the Eden U.S. Pat. No. 3,569,938, a hierarchical store is presented as being an apparent store to a using data processing system. A cache concept is shown in this patent wherein a relative high speed-access store acts as a buffer to a relatively slow access store. In this instance, a random access memory serves as a front store, or cache, while the backing store could be tape or disk storage apparatus. The size of the apparent store was the capacity of the backing store, while the access time gave an apparent access equal to the rapid access of the front store. A further hierarchical store is shown in Spencer, U.S. Pat. No. 3,839,704, wherein a direct access storage device is buffered by a random access memory which is accessible via a directory structure. A directory structure interprets the addresses for the backing direct access storage device and converts same to a buffer address through table lookup mechanisms well known in the data processing art. Again, the purpose of the Spencer arrangement was to mask a relatively long access time to the direct access storage unit. Further, Spencer provided for transferring data from the direct access storage devices to the buffer before the data processing system, connected to this hierarchical store, needed the data such that access time to the data was minimized. These two patents show general arrangements for caching various types of peripheral storage devices. Further controls are needed for satisfying modern day requirements of a paging and swapping storage system.
Another technological area in which caching enchanced performance is found in the main memory area of a computer or central processing unit. That is, each data processing system includes a central processing unit that has a cache or high-speed store. The backing store for this cache is the usual main memory. Various techniques have been used for enhancing the caching operation such that the central processing unit instruction execution as well as operand data transfers are maximized. An example of controlling the operation of the cache with respect to the central processing unit and a main memory is shown in Calle, et al., U.S. Pat. No. 4,075,686. This U.S. patent teaches that it is not always wise to use the cache--that, in some instances, performance can be enhanced by bypassing the cache. This is done in one of several ways--for example, the main memory is arranged in segments. Some of the segments may be dedicated for input/output or peripheral operations. All accesses to the segments will bypass the main memory cache. In a similar manner, the cache for a direct access storage device can be bypassed for selected devices or portions of devices under certain circumstances. In another aspect of Calle, performance enhancement can be achieved by selectively bypassing cache on a command basis. In this instance, the command to the main memory area will contain a cache bypass bit. When the bit is set to unity, the cache is not used and the main memory is directly accessed. If the cache bypass bit is reset to zero, then the cache is used. While selectively bypassing cache can, in many instances, optimize performance of the storage system, such as the main memory cache system or a DASD cache system, further controls appear to be necessary for meeting the stringent requirements of modern day paging and swapping data transfers.
In hierarchical systems there are usually several replications of the same data; that is, the backing store will contain one copy while the cache, or front store, will contain a second copy. For data integrity purposes, either the cache or the backing store can be accessed at a given instant, but not both. This limitation is implicit in the references cited above.
In a paging and swapping environment, it is desired that plural accesses be provided for multitasking paging access while minimizing host controls over the storage system; that is, the paging and swapping storage system should have a good set of controls for maximizing the host or central processing unit operations while maintaining continuity of each independent operation for ensuring integrity of the paging and swapping environment.